Chinese chip company SophGo develops 64-core RISC-V chip with firm SiFive
Where to start with RISC-V – RISC-V International
NASA Selects SiFive RISC-V CPUs to Power Future Space Computers - Jotrin Electronics
RISC-X? Top Chinese scientist discusses potential for RISC-V fork in extreme case - CNX Software
RISC-V grows open source processor membership 130% in 2021 | VentureBeat
Maxim's Arm/RISC-V Dual-Core Microcontroller | DigiKey
What is RISC-V？10 Things You Should Know About RISC-V in 2020 - Latest Open Tech From Seeed
What is RISC-V? How Open-Source ISA Shapes Future Processor Design
RISC-V: what is it all about?
RISC-V processors - Codasip
Introduction — CORE-V CV32E40P User Manual documentation
Android and RISC-V: What you need to know to be ready : r/Android
The RISC-V standards body is moving to Switzerland over fear of US trade restrictions | TechSpot
China's chip ambitions and RISC-V's open-source conundrum - EDN
How RISC-V can usurp Arm as the Switzerland of computer chips
RISC-V To Move HQ to Switzerland Amid Trade War Concerns - EE Times Europe
About RISC-V – RISC-V International
RISC-V International Ratifies 15 New Specifications Opening Up New Possibilities for RISC-V Designs | audioXpress
Renesas Unveils the First Generation of Own 32-bit RISC-V CPU Core Ahead of Competition | Business & Finance | manchestertimes.com
Leveraging RISC-V for Expedited Product Development - Axelera AI
The RISC-V standards body is moving to Switzerland over fear of US trade restrictions | TechSpot
Understanding RISC-V: The Open Standard Instruction Set Architecture
L11 RISC-V embedded processor - Codasip
Introduction — CORE-V CV32E40X User Manual documentation
